Abstract
In this article experimental results are provided for a very-large-scale integration (VLSI) floorplan design problem.Given is a set of modules to be placed non-overlapping on a 2-dimensional rectangular plane.We use ant system simulation as a heuristics to produce feasible layouts in order to minimize the total unused area.The algorithm differs from many others in that fact that it produces non-slicing floorplan.Our experimental results show comparable results of previous methods using ant colony optimization (ACO) in VLSI design.For this purpose we define the "interior" structure for a geometrical computation of module positions.