On-chip measurements of standard-cell propagation delay

2010

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DOI 10.1109/ewdts.2010.5742113
Data confidence 70 medium
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Abstract

We report on implementation of random sampling methodology for on-chip measurements of the pin-to-pin propagation delay of single standard cells of core library. A test chip has been implemented in 0.13 μm GL130SB (130 nm Logic Process) technology at Dongbu HiTek and used to monitor up to picosecond's timing behavior of 32 DUT's of core library. Observed mismatch between simulated and measured parameters helps to improve and verify library cell models.