Abstract
The paper is devoted to the study of hardware realization of division algorithms for their implementation in FPGA. Verilog descriptions of the module that performs division using the algorithm without restoring the remainder and the device that implements the Newton–Raphson division method were prepared for the study. Implementations were compared in terms of performance and hardware costs. Analysis of the results showed the advantages of the hardware implementation of the Newton–Raphson division method. In addition, a comparison of modules with the division unit based on the application of LPM CAD Quartus Prime was carried out, it showed the effectiveness of algorithmic solutions.