Design of CMOS-memristor Circuits for LSTM architecture

2018

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DOI 10.1109/edssc.2018.8487179
Data confidence 70 medium
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Abstract

Long Short-Term memory (LSTM) architecture is a well-known approach for building recurrent neural networks (RNN) useful in sequential processing of data in application to natural language processing. The near-sensor hardware implementation of LSTM is challenged due to large parallelism and complexity. We propose a 0.18 μm CMOS, GST memristor LSTM hardware architecture for near-sensor processing. The proposed system is validated in a forecasting problem based on Keras model.