Abstract
A hardware implementation of a high-speed device for reducing numbers modulo is considered. We used a modified division algorithm with a shift of the dividend, where at each step n + 3 most significant bits of the dividend, and then the resulting remainders, participate. The shift of the reduced number at each step by three bits to the left towards the higher bits shifted and it makes it possible to speed up the process of reduction in modulus by reducing the number of modular reduction steps. The main unit of the device is a block of partial remainder formers (PRFs), which use subtraction of the P modulus and multiples of the P modulus.