Abstract
This paper would explain in detail the design of an In-phase-Quadrature (I/Q) demodulator with low current consumption. SiGe 0.35μ$m$BiCMOS technology with fT =45 GHz,fmax = 60 GHz and Noise Figure = 0.8 dB at 2GHz was used for the design. The CMOS devices were primarily used in the biasing circuits for power consumption reduction, whereas SiGe Bipolar devices were used in signal path circuits. The design contained two mixers, a local oscillator (LO) divider, a bias/control circuit, a negative resistance circuit, and buffer amplifiers. The I/Q demodulator was then layout and had gone through the post-layout simulation to check performance with the parasitic elements introduced from the layout. A prototype was measured and was found to be agreed with the simulation results. The prototype was tested in the region of 190 MHz input frequency and output frequency of 0–35 MHz. In addition, the prototype had also met the specifications for the non-contact vital sign I/Q demodulator. It achieved an EVM of 2.9%. It was also achieved a gain ripple of 0.12 dB, gain mismatch of 0.1 dB, and phase mismatch of 1.25°. The design, consisting of mixers, frequency dividers, buffer amplifiers, and bias/control circuits, consumes 4 mA with a 3V power supply. With the AGC and VGA, the total current is 11 mA. The maximum IIP3 is -9 dBm.