Abstract
Many computer systems for calculating the proper organization of memory are among the most critical issues. Using a tier cache memory (along with branching prediction) is an effective means of increasing modern multi-core processors' performance. Designing high-performance processors is a complex task and requires preliminary verification and analysis of the model level, usually used in analytical and simulation modeling. The refinement of extreme programming is an unfortunate challenge. Few experts disagree with the synthesis of access points. This article demonstrates that Internet QoS and 16-bit architectures are always incompatible, but it's the same situation for write-back caches. The solution to this problem can be implemented by analyzing simulation models of different complexity in combination with the analytical evaluation of individual algorithms. This work is devoted to designing a multi-parameter simulation model of a multi-process for evaluating the performance of cache memory algorithms and the optimality of the structure. Optimization of the structures and algorithms of the cache memory allows you to accelerate the interaction of the memory process and improve the performance of the entire system.