HSTL IO Standards Based Low Power Implementation of Elliptic Curve Cryptography (ECC) on FPGA

2024

Closed access Metadata (CSL-JSON)
DOI 10.1109/sist61555.2024.10629505
Data confidence 70 medium
How this score is calculated

It is built from checkable properties of the record itself: whether the article has a DOI, how many independent sources confirmed its data, whether the required fields are filled in, and how recent the latest confirmation is. Disagreement between sources and a missing identifier lower it. A value of 80 or above means the record was published without further checking; 60 to 79 means it is published at reduced confidence, with a manual check advisable. A record verified by an editor by hand is never pushed below 90 by a recalculation. This scores our data about the article, not the article itself.

Abstract

There is a new trend in researcher to use elliptical curve theory for derivation of an efficient, faster and smaller key that will use in lightweight cryptography also known as elliptical curve cryptography (ECC). In this work, we are using High Speed Transceiver Logic (HSTL) IO standard to develop an energy efficient ECC and implementing the Hardware Description Language (HDL) code of ECC on Kintex-7 Field Programmable Gate Array (FPGA). HSTL_II_18 is taking 53.73 % more power in comparison to HSTL_I IO standards. The implementation with HSTL_I or HSTL_II_18 will deliver same result of encryption but power requirement will change. Wise selection of IO standards playing an important role in overall power dissipation during implementation of ECC on FPGA.