A dynamically reconfigurable VLSI processor with hierarchical structure based on a micropacket transfer scheme

Yoshichika Fujioka, Michitaka Kameyama, Martin Lukáč

2017

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DOI 10.1109/dt.2017.8024284
Data confidence 70 medium
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Abstract

In this paper we propose improvements to the Micro-packet Transfer scheme in a multi-core device (also called reconfigurable VLSI or Network-on-chip). In particular we propose a new hierarchy based micro-packet control scheme that is especially effective for tasks require large number execution clock steps.