Abstract
This paper presents a face recognition method implemented using reconfigurable network of memristive threshold logic cells that can be practically realised in a secondary plane to the pixel arrays. Among the most distinguishing features of the presented system are a) an early detection and storage of only the relevant information directly from the sensors, b) a parallel, scalable information storage and detection architecture in hardware, as opposed to an algorithmic approach, and c) a fast and robust face recognition system. The threshold logic cell is inspired from a simplistic cortical neuron model that has multiple inputs with corresponding input memristors and one binary output. These cells when used with a set of input memristors are able to detect significant pixel variations in the incoming video frame and memorize the output template depending on the logic of selection of the resistor values. The implemented face recognition circuit shows small chip area, low power dissipation and ability to scale the networks with increase in image resolutions.