Abstract
Purpose – The purpose of this paper is to present a new approach to edge detection using semiconductor flash memory networks having scalable and parallel hardware architecture. Design/methodology/approach – A flash cell can store multiple states by controlling its voltage threshold. The equivalent resistance of the operation states controlled by threshold voltage of flash cell gives out different combinations of logic 0 and 1 states. The paper explores this basic feature of flash memory in designing a resistance change memory network for implementing novel edge detector hardware. This approach of detecting the edges is inspired from the spatial change detection ability of the human visual system. Findings – The proposed approach consumes less number of electronic components for its implementation, and outperforms the conventional approaches of edge detection with respect to the processing speed, scalability and ease of design. It is also demonstrated to provide edges invariant to changes in the direction of the spatial change in the images. Research limitations/implications – This research brings about a new direction in the development of edge detection, in terms of developing high-speed parallel processing edge detection and imaging circuits. Practical implications – The proposed approach reduces the implementation complexity by removing the need to have convolution operations for spatial edge filtering. Originality/value – This paper presents one of the first edge detection approaches that is purely a hardware oriented design, uses resistance of flash memory to form edge detector cells, and one that does not use computational operations such as additions or multiplications for its implementation.