Abstract
Urban intersections require deterministic, fast and adaptable signal control because fixed-time controllers cannot respond efficiently to directional traffic imbalance, pedestrian requests or emergency conditions. This methodology paper presents an FPGA-based real-time traffic signal control architecture in which synchronized sensor inputs are processed by a finite-state machine (FSM), adaptive green-time logic and hardware safety interlocks. The proposed design is expressed in synthesizable HDL and is organized into sensor-conditioning, queue-estimation, phase-control, timing, pedestrian-priority and output-driver modules. A controlled numerical intersection model was used to evaluate the control strategy before hardware deployment. Four one-hour traffic scenarios were generated using Poisson arrivals for north–south and east–west approaches. Under highly unbalanced demand, the adaptive controller reduced mean queueing delay from 159.3 s to 30.8 s for north–south-heavy traffic and from 185.9 s to 32.3 s for east–west-heavy traffic, while maintaining approximately 99% vehicle service. The methodology also enforces mutually exclusive green phases, fixed yellow clearance and bounded minimum/maximum green times. The results indicate that FPGA logic is well suited to real-time traffic control where deterministic timing, parallel input processing and reconfigurability are required. The paper focuses on methodology and simulation-based verification rather than field deployment.