Abstract
Deterministic execution latency is a critical requirement for arithmetic units deployed in real-time and safety-critical digital systems.Conventional radix-4 digit-recurrence dividers generate successive quotient digits through dependent iterations; although pipelined tatations improve throughput, they retain multi-cycle latency, pipeline registers, and control logic, limiting their suitability for applications that demand predictable timing.This paper presents a fully combinational (arrayorganized) radix-4 digit-recurrence divider in which the recursive digit dependency is mapped onto a fixed-depth cascade of identical combinational stages, yielding single-cycle, operand-independent latency while preserving the radix-4 arithmetic formulation unchanged.We refer to this transformation as spatial unfolding.Three architectural features keep the fully spatial realization compact.The divisor multiples B, 2B and 3B and their complements are generated once and broadcast to all stages.Quotient selection is performed by parallel comparators, avoiding lookup tables.Subtraction is realized as complement-add that reuses the comparator outputs, removing dedicated subtractor circuitry.The architecture was described in parameterized Verilog HDL and implemented on a Xilinx Artix-7 XC7A100T-1CSG324C FPGA for operand widths from 8 to 32 bits.It attains operating frequencies from 57.14 MHz (8-bit) to 16.95 MHz (32-bit), occupies only 53-1080 LUTs and 24-98 flip-flops with no DSP blocks or embedded memory, and dissipates 0.010-0.020W