Abstract
Public-key cryptography solves the problem of key distribution, which is inherent in symmetric cryptography. However, there are problems associated with the high resource consumption of such crypto algorithms, which necessitates new methods to increase speed. The work is dedicated to the development of devices that perform modular square- building, which is one of the basic operations in the implementation of public-key cryptosystems. The resolution of the implementation approach is being analyzed. The method is considered where the multiplication of a number by bits thereof is carried out starting from its senior digits. Two variants are proposed for the implementation of the central unit of the Partial Residue Shaper (PRF). The workability of the developed devices has been tested on the FPGA Artix-7 using the Verilog hardware description language.