Abstract
The paper presents the development and optimization of a hybrid hardware-software implementation of the post-quantum cryptographic algorithm Saber on an embedded CPU-FPGA platform. The main objective of the research is to enhance the performance, energy efficiency, and security of post-quantum key exchange schemes under limited computational resources while maintaining resistance to side-channel attacks.The proposed architecture integrates the computational capabilities of the ARM processor and the FPGA core, enabling efficient distribution of workloads between the processor and the hardware accelerator.The hardware part implements pipelined polynomial multiplication and SHA-3 hashing, while the software component manages data flow, synchronization, and integrity control. A fixed-latency communication interface between the CPU and FPGA ensures constant-time execution and stability against timing variations.Three implementations of the algorithm were compared: software, hardware, and hybrid. Experimental results demonstrated a 35-50% reduction in execution time without compromising cryptographic strength or increasing power consumption. A TVLA (Test Vector Leakage Assessment) analysis confirmed the absence of any statistical correlation between the energy profile and secret data, validating the system’s side-channel resistance.The proposed solution can be effectively applied to mobile robotic platforms, unmanned marine vehicles, industrial telemetry networks, and IoT systems requiring high-performance and quantum-resistant data protection.