Аннотация
The concept of a pseudo-resistive threshold logic circuit that uses a combination of CMOS inverter and bulk driven MOSFET pseudo-resistive divider circuit for designing a universal NOR gate is presented. Inspired from the neuronal firing mechanisms, the inverter implements the binary threshold decision, while pseudo-resistive circuit provides the summation of normalised weighted inputs. The proposed logic gate when tested using the TSMC 0.18 µm low voltage process show an overall improved performances in terms of area, delay and power in comparison with CMOS and pseudo NMOS logic.