Аннотация
This tutorial overviews reconfigurable hardware accelerators that have been proposed for data processing in high-performance computing systems. They are based on different kinds of networks (sorting, searching, counting, etc.) and recur to iterative implementations that allow the required hardware resources to be significantly reduced almost without compromising the respective processing times. The accelerator architectures are first modelled in software and then implemented in reconfigurable hardware. The results of experiments are reported and references are given to more detailed descriptions of all the design and validation steps.