Аннотация
Integer division remains one of the most computationally demanding arithmetic operations in digital computing systems. Conventional sequential dividers produce one quotient bit per clock cycle, requiring n cycles for an n-bit division. This paper proposes an architecture for a sequential integer divider capable of simultaneously generating three quotient bits per clock cycle. The proposed device comprises a dividend register (DR), a divisor multiples generator (DMG), a partial remainder and quotient digit generator (PRQDG), and a synchronization unit (SU). Unlike classical SRT dividers, which rely on a redundant quotient representation and quotient-digit selection tables, the proposed architecture performs an exact comparison of the partial remainder against the precomputed divisor multiples B-7B, thereby eliminating the growth of the selection table as the radix increases. The architecture is described in Verilog HDL and verified on a Xilinx Artix-7 FPGA using the Vivado design suite. The prototype for a 12-bit dividend and a 6-bit divisor occupies 158 LUTs and 50 flip-flops, attains a maximum clock frequency of 134.6 MHz, and is confirmed by a suite of ten tests; a division is completed in two clock cycles. The architecture is intended for use in high-speed digital computing units and specialized processors.